(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method of fabricating a capacitor under bit line (CUB), structure, for a dynamic random access memory (DRAM, device.
(2) Description of Prior Art
The continuing increase in the density of DRAM cells, achieved via micro-miniaturization, or the ability to fabricate devices with sub-micron features, has led to difficulties in achieving the desired capacitance for an individual DRAM device. The horizontal dimensions of a stacked capacitor structure, used in each DRAM device, in now limited by the decreasing size, or width, of the DRAM device, thus placing greater demands on increasing the height, or vertical dimension of the stacked capacitor structure, to provide the needed surface area and thus the needed capacitance. However increasing the vertical dimensions of the DRAM, stacked capacitor structure, results in the use of thicker insulator layers, used to accommodate deeper capacitor openings, and to provide adequate passivation for the underlying stacked capacitor structure. The use of thicker insulator layers in turn, result in added process complexity in terms of an increased aspect ratio for the dry etched, narrow diameter bit line contact holes, used in the CUB DRAM designs. In addition the decreased spacing between the stacked capacitor structure and the bit line structure, can lead to electrical leakage or shorts between these key DRAM elements.
This invention will describe a novel method of fabricating a CUB DRAM device, in which the aspect ratio of the dry etched, bit line contact hole is not increased as a result of increasing vertical dimensions of the capacitor structure. In addition this invention will teach a method of providing insurance against leakage, or shorts, that can occur between the bit line contact structure and the capacitor structure. Prior art, such as Tseng, in U.S. Pat. No. 5,926,710, presents a fabrication procedure for a stacked capacitor structure, while Jost et al, in U.S. Pat. No. 6,110,774, show a fabrication procedure for a capacitor under bit line capacitor structure. However these prior arts do not use the novel process steps and process sequences, presented in the present invention, which allow a reduction in bit line contact hole aspect ratio, and improved isolation between the bit line and capacitor structures, to be realized.